ACL Digital | Senior Physical Design Engineer

ACL Digital • san jose, ca, us • 5h ago

W2 Only

Skills:

Full chip and Block constraints development and constraints generation.
Full chip and Block Synthesis, STA and timing closure using Primetime and DMSA flow
Run and debug Formality and VCLP Tools
Interfacing with internal external teams including Design, IP, Library
Methodology & Flow development of Synthesis, Formality, STA & Timing Closure

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